1. Filed of the Invention
The field of the present invention relates to electrostatic discharge protection circuits; and in particular to an electrostatic discharge (xe2x80x9cESDxe2x80x9d) protection circuit with enhanced input protection performance employing a reduction in an input isolation resistor.
2. Description of Related Art
ESD results when an electrostatic charge is dissipated either to another object or to ground rapidly, resulting in a high voltage pulse. In an integrated circuit (IC) environment, equipment and personnel can acquire substantial amounts of electrostatic charge that can subsequently be transferred to an integrated circuit during manufacturing or during usage. The human body, for example, can accumulate charges exceeding 2000V, which if discharged to the IC could cause damage to it.
Damage to a device during an ESD event is determined by the device""s inability to dissipate the energy of the discharge by withstanding the voltage levels involved. This is known as the device""s xe2x80x9cESD sensitivity.xe2x80x9d Many electronic components are susceptible to ESD damage even at relatively low voltage levels.
As integrated circuit devices become smaller, ESD damage is more likely to occur because of the devices inability to safely dissipate the discharge. When an electronic device experiences an ESD, it may no longer function because the discharge may have caused for example one or more of a metal melt down, a junction breakdown, and an oxide failure. If the device does not fail after encountering an ESD, the exposure may result in a degradation the device. The degradation may involve impairment of the devices""s functions or a decrease in the device""s operating life.
Conventional approaches to the ESD problem have been to provide the protected circuit with devices that can intervene to shunt ESD charges to ground. Two-stage protection comprising a primary protection device and a secondary protection device, as shown in FIG. 1, is the conventional input protection scheme. In a conventional scheme the primary protection device will shunt most or all of the current during ESD, while the secondary element functions to limit the voltage or current seen by the protected circuit until the primary device is fully operational. The trigger voltage of the secondary protection device is generally lower than the trigger voltage of the primary protection device. For example, FIG. 7(A) depicts an I-V curve of such a conventional two-stage protection device. The trigger voltage Vtr2 of the secondary protection device is shown to be about 8.6V in the figure. After the operational voltage reaches the trigger voltage of the secondary protection device, the ESD current flows through the isolation resistor between the primary and secondary protection devices. The voltage drop (Ixc3x97R) increases the pad voltage, as depicted by the linear I-V region LR after the 8.6V level of FIG. 7(A). When the pad voltage increases to approximately 13.4V, which is the trigger voltage of the primary protection device, the primary protection device is triggered to discharge the ESD current, reaching a peak current P in the graph.
In a conventional scheme, the trigger voltage of the protection device is fixed. In order for the primary protection device be triggered as soon as possible, a large isolation resistor is required to increase the pad voltage faster during an ESD event. For performance enhancement of the input protection, this isolation resistor has a low limit on the order of 100 to 150 ohms, depending on the process. The isolation resistor becomes the input resistor to the internal circuit of the IC and reduces the speed of the internal circuit. The effect of the isolation resistor is especially pronounced for high-speed integrated circuits.
Therefore, it is desirable to produce a new scheme to reduce the input resistance without sacrificing the performance of the protection circuit.
In the present invention, a new apparatus and method to reduce the input resistance of an ESD protection circuit is presented. An ESD protection circuit, comprising a primary protection device, a secondary protection device, and a pickup node, is connected between an input pad and an internal circuit for protecting an internal circuit from being damaged by an ESD current. The new apparatus and method is directed to reducing the trigger voltage of the primary protection device by implementing primary and secondary protection devices which share a common source region. The primary protection device comprises a drain, a source, a channel region between the source and the drain, and a gate structure (in some embodiments, no conductive gate is needed) over the channel region in a semiconductor body. The secondary protection device comprises a gate, a channel, a drain, and shares its source with the primary protection device.
The secondary protection device also has gate structure on top of the channel region between its drain and the shared source. The gates of the primary and secondary protection devices are connected to the common source region and to ground. The drain regions of both the primary and secondary protection devices are connected to the protected terminal(s). In addition, there is a substrate pickup within the protection structure, comprising diffused or implanted materials of the same conductivity type as the surrounding semiconductor body. In the preferred embodiment, the substrate pickup is disposed next to the secondary protection device rather than the primary protection device.
A variety of devices, including, but not limited to, thin-gate NMOS devices, can serve as primary and secondary protection devices. In one embodiment, the primary protection device comprises field-oxide device and the secondary protection device comprises a grounded-gate NMOS (GGNMOS). In another embodiment, the primary protection device comprises a thin-gate NMOS with the gate length longer than that of the secondary protection device, which also comprises a thin-gate NMOS. In yet another embodiment, the primary protection device comprises the low-voltage SCR and the secondary protection device comprises a NMOS. In yet another embodiment, the primary protection device comprises the low-voltage SCR and the secondary protection device comprises a diode.
The present invention is applicable to, but is not limited to, output pads and power pads. However, because of the large area involved for the two-stage protection structure, the protected terminals most commonly comprise input pads.
In summary, under the common source implementation, the trigger voltage of the primary protection device will be lowered significantly; it may be substantially equal to the trigger voltage of the secondary protection device. As the trigger voltage of the primary protection device decreases, the resistance of the isolation resistor can be reduced accordingly and theoretically to zero, thus eliminating the need for an isolation resistor, which interferes with the performance of the protected circuit.
Additional features and advantages of the invention will be set forth in the detailed description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The aspects and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention can be characterized according to one aspect as an electrostatic discharge (ESD) protection circuit for protecting terminals of an integrated circuit on a semiconductor body, including a primary protection device formed in said semiconductor body, a secondary protection device formed in said semiconductor body, wherein the primary protection device and the secondary protection device share a diffusion region, and a grounded pickup region adjacent to one of the primary and the secondary protection devices.
Another aspect of the present invention can be characterized as a method for making an electrostatic protection circuit, having a reduced isolation resistance, for protecting an integrated circuit, the method including the steps of forming a primary protection device in a semiconductor body, forming a secondary protection device in a semiconductor body, wherein the primary protection device and the secondary protection device share a diffusion region, and forming a grounded pickup region adjacent to one of the primary and the secondary protection devices.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.